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ADE7518
TIMING SPECIFICATIONS
AC inputs during testing were driven at V SWOUT ? 0.5 V for Logic 1
and 0.45 V for Logic 0. Timing measurements were made at V IH
minimum for Logic 1 and V IL maximum for Logic 0, as shown in
Figure 2.
For timing purposes, a port pin is no longer floating when a
100 mV change from load voltage occurs. A port pin begins to
float when a 100 mV change from the loaded V OH /V OL level
occurs, as shown in Figure 2.
For Table 4 to Table 9, C LOAD = 80 pF for all outputs, V DD = 2.7 V to
3.6 V, and all specifications T MIN to T MAX , unless otherwise noted.
V SWOUT – 0.5V
0.45V
0.2V SWOUT + 0.9V
TEST POINTS
0.2V SWOUT – 0.1V
V LOAD – 0.1V
V LOAD
V LOAD + 0.1V
TIMING
REFERENCE
POINTS
V LOAD – 0.1V
V LOAD
V LOAD – 0.1V
Figure 2. Timing Waveform Characteristics
Table 4. Clock Input (External Clock Driven XTAL1) Parameters
32.768 kHz External Crystal
Parameter
t CK
t CKL
t CKH
t CKR
t CKF
1/t CORE
Description
XTAL1 period
XTAL1 width low
XTAL1 width high
XTAL1 rise time
XTAL1 fall time
Core clock frequency 1
Min
0.032768
Typ Max
30.52
6.26
6.26
9
9
1.024 4.096
Unit
μs
μs
μs
ns
ns
MHz
1
The ADE7518 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal clock for the system.
The core can operate at this frequency or at a binary submultiple defined by the CD[2:0] bits, selected via the POWCON SFR (see Table 24).
Table 5. I 2 C-Compatible Interface Timing Parameters (400 kHz)
Parameter
t BUF
t L
t H
t SHD
t DSU
t DHD
t RSU
t PSU
t R
t F
t SUP1
Description
Bus-free time between stop condition and start condition
SCLK low pulse width
SCLK high pulse width
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Rise time of both SCLK and SDATA
Fall time of both SCLK and SDATA
Pulse width of spike suppressed
Typ
1.3
1.36
1.14
251.35
740
400
12.5
400
200
300
50
Unit
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
1
Input filtering on both the SCLK and SDATA inputs suppresses noise spikes of less than 50 ns.
t BUF
t SUP
t R
SDATA (I/O)
t PSU
t DSU
t SHD
MSB
t DHD
LSB
t H
t DSU
ACK
t RSU
t DHD
MSB
t F
t R
SCLK (I)
PS
1
2 TO 7
t L
8
t SUP
9
S(R)
t F
1
STOP START
CONDITION CONDITION
Figure 3. I 2 C-Compatible Interface Timing
Rev. 0 | Page 9 of 128
REPEATED
START
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